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Telecommunication Systems Institute (TSI), Greece
Telecommunication Systems Institute
Role: TSI is the coordinator of the project. Moreover, TSI is mainly be involved in the design and implementation of the UNIMEM and UNILOGIC hardware architecture. TSI will built the final 256-core heterogeneous prototype, which can be accessed by the other partners via the internet.
Key Personel: Iakovos Mavroidis

Queen's University Belfast (QUB), United Kingdom
Queen's University Belfast
Role: QUB leads the effort in system software where the QUB team leverages its significant prior experience with design, development and deployment of production-strength HPC software on supercomputing infrastructures. QUB will contribute significantly to the application requirements specification and system specification by leveraging its experience with real-world HPC applications on supercomputers in Europe (HECTOR, ARCHER) and the US (LLNL, ORNL, NCSA).
Key Personel: Dimitrios S. Nikolopoulos

STMicroelectronics (STM), France
Role: ST is mainly involved in the design and implementation of the NoC that will be used in the compute nodes as well as in the ECOSCALE system-level hierarchical topology. ST will use its STNoC communication infrastructure adapting it to the needs of ECOSCALE. Moreover, ST will provide the requirements of the HPC systems contributing to the specifications of the hardware system and the programming model.
Key Personel: Marcello Coppola

Acciona (ACC), Spain
Role: The contribution of ACCIONA to the ECOSCALE project is focused on its role as developer and integrator of a smart city application based on computer vision which will be used as one of the use cases to be executed for testing the framework which is going to be developed within the project.
Key Personel: Jose Luis Buron

University of Manchester (MAN), United Kingdom
University of Manchester
Role: MAN will develop the physical implementation backend tool chain that will take the results from the high-level synthesis tool in order to generate the reconfigurable hardware accelerator module library. In addition, MAN will contribute to the integration phase by providing a communication architecture that will allow multiple accelerator modules to be integrated and connected within in the same reconfigurable resource area of the FPGA. For managing and virtualizing the reconfigurable resources of the workers at runtime, MAN will design and implement the necessary low level services.
Key Personel: Dirk Koch and John Goodacre

Politecnico di Torino (POLITO), Italy
Politecnico di Torino
Role: POLITO will mostly work on the core functionality of FPGA synthesis and mapping environment. POLITO will focus on the OpenCL-to-FPGA synthesis tool and the simulation framework. Moreover, it will also be involved in the development of the simulation model that will be used to optimize various aspects of the architecture.
Key Personel: Luciano Lavagno

Chalmers University of Technology (CHAL), Sweden
Chalmers University of Technology
Role: The main activity of Chalmers in ECOSCALE is on the proposed HPC architecture that enables managing and sharing the reconfigurable acceleration blocks. Chalmers also contributes on runtime system management.
Key Personel: Ioannis Sourdis and Vassilis Papaefstathiou

Synelixis (SYN), Greece
Role: Synelixis will develop a novel oil-field simulation, which is a demanding HPC application. Synelixis will also be responsible for the simulation model of a full-scaled ECOSCALE system.
Key Personel: Ioannis Papaefstathiou

FORTH, Greece
Role: FORTH designed the base board for the ECOSCALE prototype. The board can host up to eight interconnected ExaNeSt compute nodes (called QFDBs) each one supporting 4 FPGAs. Moreover, FORTH has provided the ExaNeSt compute nodes for the prototype.
Key Personel: Manolis Katevenis
Contact Info

Iakovos Mavroidis

Telecommunication Systems Institute (TSI)

Electronic and Computer Engineering Department

Technical University of Crete (TUC)
Chania, GR-73100, Greece

Tel.: +302810254899


Seventh Framework Programme