Press Center

Publications

  • I. Mavroidis, I. Papaefstathiou, L. Lavagno, D. S. Nikolopoulos, D. Koch, J. Goodacre, I. Sourdis, V. Papaefstathiou, M. Coppola, M. Palomino, "ECOSCALE: Reconfigurable Computing and Runtime System for Future Exascale Systems", DATE 2016, Dresden, Germany [paper]
  • P. Harvey, K. Bakanov, I. Spence, D. S. Nikolopoulos, "A Scalable Runtime for the ECOSCALE Heterogeneous Exascale Hardware Platform", Association for Computing Machinery (ACM), 2016 [paper]
  • Muslim, F. B., Demian, A., Ma, L., Lavagno, L., Qamar, A., "Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL" , In Proceedings of the Federated Conference on Computer Science and Information Systems (FedCSIS ¡2016). [paper]
  • Ma, L., Muslim, F. B., and Lavagno, L., "High performance and low power monte carlo methods to option pricing models via high level design and synthesis" , In Proceedings of the 10th European Modelling Symposium on mathematical modelling and computer simulation (EMSB 2016). [paper]
  • Muslim, F. B., Ma, L., Roozmeh, M., and Lavagno, L., "Efficient FPGA Implementation of OpenCL High-Performance Computing applications via High-Level Synthesis", IEEE Access. [paper]
  • K. Pham, E. Horta and D. Koch, "BITMAN: A Tool and API for FPGA Bitstream Manipulations" , DATE 2017, Lausanne, Switzerland, 2017.
  • E. Horta, X. Shen, K. Pham and D. Koch, "Accelerating Linux Bash Commands on FPGAs Using Partial Reconfiguration" FSP 17 (co-located with FPL), 2017.
  • A. Malek, E. Vasilakis, V. Papaefstathiou, P. Trancoso and I. Sourdis, " Odd-ECC: On-demand DRAM Error Correcting Codes", Int. Symp. on Memory Systems (MEMSYS), ACM, 2017.
  • S. Tzilis, M. Pericas, P. Trancoso and I. Sourdis, "SWAS: Stealing Work using Approximate System-load Information", 3th Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS), held together with Int. Conf. on Parallel Pro- cessing (ICPP), ACM, 2017.
  • R. Garcia and D. Koch, "On the HLS Design of Bit-Level Operators and Custom Data Types" ,FSP 17 (co-located with FPL), Ghent, Belgium, 2017.
  • E. Horta, X. Shen, K. Pham, and D. Koch, "Accelerating Linux Bash Commands on FPGAs Using Partial Reconfiguration", FSP2017 workshop, Ghent, Belgium.
  • E. Vasilakis, V. Papaefstathiou, P. Trancoso and I. Sourdis, "FusionCache: using LLC Tags for DRAM Cache", IEEE Design, Automation, and Test in Europe (DATE), Dresden, Germany, March, 2018.
  • Maria Papadogiorgaki, Panagiotis Koliou and Michalis E. Zervakis, "Glioma Growth Modeling based on the Effect of Vital Nutrients and Metabolic Products, Medical & Biological Engineering & Computing, Springer, pp 1-15, March 2018. DOI: 10.1007/s11517-018-1809-0.
  • P. Malakonakis, K. Georgopoulos, A. Ioannou, L. Lavagno, I. Papaefstathiou, I. Mavroidis, "HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE", Applied Reconfigurable Computing. Architectures, Tools, and Applications, pp.724-736, January 2018.
  • K. Georgopoulos, A. Ioannou, P. Malakonakis, I. Mavroidis, V. Papaefstathiou, I. Sourdis, "UNIMEM and UNILOGIC architectures for local/remote sharing of resources", ExascaleHPC Workshop, Manchester, Jan. 2018
  • A. Arif, F. Barrigon, F. Gregoretti, J. Iqbal, L. Lavagno, M. Lazarescu, L. Ma, M. Palomino, J. Segura, " Performance and energy-efficient implementation of a smart city application on FPGAs" , Journal of Real-Time Image Processing, May 2018.
  • P. Malakonakis, K. Georgopoulos, A. Ioannou, L. Lavagno, I. Papaefstathiou and I. Mavroidis, "HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware", PRACEdays18, European HPC Summit Week, May 2018.
  • A. Ejaz, V. Papaefstathiou, I. Sourdis, "DDRNoC: Dual Data-Rate Network-on-Chip", ACM Transactions on Architecture and Code Optimization (TACO), 15, 2, Article 25, June 2018.
  • G. Bogdan, C Kritikakis, and D Koch, "HLS Enabled Partially Reconfigurable Module Implementation", ARCS 2018, Brunswick, Germany.
  • Vaishnav, K. D. Pham, and D. Koch, "A Survey on FPGA Virtualization", FPL 2018, Dublin, Ireland, August 2018.
  • A. Vaishnav, K. D. Pham, D. Koch, and J. Garside, "Resource Elastic Virtualization for FPGAs using OpenCL", FPL 2018, Dublin, Ireland, August 2018
  • K. D. Pham, A. Vaishnav, M. Vesper, and D. Koch, "ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications", FSP 2018 (co-located with FPL 2018), Dublin, Ireland
  • A. Vaishnav, K. D. Pham, and D. Koch, "Live Migration for OpenCL FPGA Accelerators", FPT 2018, Okinawa, Japan, 2018.
  • K. D. Pham, E. Horta, D. Koch, A. Vaishnav, and T. Kuhn, "IPRDF: an Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs", MCSoC 2018, Hanoi, Vietnam, 2018.
  • A. Ejaz, V. Papaefstathiou and I. Sourdis, "FreewayNoC: A DDR NoC with Pipeline Bypassing", 12th IEEE/ACM Int. Symp. on Networks-on-Chip (NOCS 2018), Torino, Italy, October, 2018 (nominated for best paper award).
  • K. Georgopoulos, I. Mavroidis, L. Lavagno, I. Papaefstathiou, K. Bakanov, "Energy-Efficient Heterogeneous Computing at exaSCALE - ECOSCALE", Hardware Accelerators in Data Centers, pp. 199, Springer Book, 2018.
  • A. Ioannou, P. Malakonakis, K. Georgopoulos, I. Papaefstathiou, I. Mavroidis, A. Dollas, "FPGA accelerator optimizations for Diversified Oil Reservoir Simulation Algorithms", AccelCloud: Workshop and Contest on Accelerating Big Data in Heterogeneous Cloud computing, HiPEAC'19 Conference, Valencia, Jan. 2019 (Contest Winner)
  • A Ioannou, K. Georgopoulos, P. Malakonakis, I. Mavroidis, I. Papaefstathiou, "ECOSCALE - Towards HPC based on the UNILOGIC architecture and a novel interconnect/addressing scheme for global resource sharing", Towards European Exascale HPC Workshop at the HiPEAC'19 Conference, Valencia, Jan. 2019.
  • E. Vasilakis, V. Papaefstathiou, P. Trancoso and I. Sourdis, "Decoupled Fused Cache: fusing a decoupled LLC with a DRAM cache", ACM Transactions on Architecture and Code Optimization (TACO), Volume 15 Issue 4, No. 65, January, 2019.
  • K. Georgopoulos, A. Ioannou, P. Malakonakis, K. Pham, K. Bakanov, D. Koch, L. Lavagno, I. Mavroidis, I. Papaefstathiou, "A Novel Framework for Utilising Multi-FPGAs in HPC Systems", Taylor & Francis Group, in print, 2019.
  • K. D. Pham, M. Vesper, D. Koch, and E. Hung, "EFCAD - an Embedded FPGA CAD Tool Flow for Enabling On-Chip Self-Compilation", FCCM 2019, San Diego, USA, 2019.
  • A. Vaishnav, K. D. Pham, D. Koch, "Heterogeneous Resource-Elastic Scheduling for CPU+ FPGA Architectures", HEART 2019, Nagasaki, Japan, 2019.
  • K. Manev, A. Vaishnav, C. Kritikakis, D. Koch, "Scalable Filtering Modules for Database Acceleration on FPGAs", HEART 2019, Nagasaki, Japan, 2019.
  • E. Vasilakis, V. Papaefstathiou, P. Trancoso and I. Sourdis, "LLC-guided Data Migration in Hybrid Memory Systems", 33rd IEEE Int'l Parallel and Distributed Processing Symposium (IPDPS), Rio de Janeiro, Brazil, May, 2019.
  • C. Kritikakis, D. Koch, "End-to-end Dynamic Stream Processing on Maxeler HLS Platforms", ASAP 2019, New York, USA, 2019.

Book Chapters

  • Konstantinos Georgopoulos, Iakovos Mavroidis, Luciano Lavagno, Ioannis Papaefstathiou, Konstantin Bakanov, "Energy-Efficient Heterogeneous Computing at exaSCALE-ECOSCALE", Hardware Accelerators in Data Centers 2019, Springer.
  • K. Georgopoulos, K. Bakanov, I. Mavroidis, I. Papaefstathiou, A. Ioannou, P. Malakonakis, K. Pham, D. Koch, L. Lavagno, "A Novel Framework for Utilising Multi-FPGAs in HPC Systems", Heterogeneous Computing Architectures: Challenges and Vision 2019, Taylor & Francis Group.

Events, Talks, Demos and Presentations

  • 30 Sept 2015: Project presentation, ETP4HPC, Rome [presentation]
  • 20 Jan 2016: Poster presentation, HiPEAC 2016, Prague [poster]
  • 15-17 March 2016: Booth excibition, DATE 2016, Dresden [link]
  • 10 May 2016: EXDCI workshop, 2016, Prague [link]
  • 11 May 2016: Poster Presentation, Pracedays16, 2016, Prague [link]
  • 12 May 2016: ETP4HPC ESD workshop, 2016, Prague [link]
  • 19 Sep 2016: EuroEXA workshop, Trieste
  • 7 Nov 2016: EuroEXA workshop, HiPEAC CSW, Dublin
  • 24 Jan 2017: NEXT (Novel EXascale computing system Technologies), Stockholm
  • 25 Jan 2017: HiPEAC conference, Stockholm
  • 17 March 2017: Joint ECOSCALE-ExaNeSt workshop, Rome
  • 29 March 2017: DATE 2017, Lausanne
  • 16 March 2017: Pracedays 17, Barcelona
  • 27 March 2017: EU-HPC workshop, HiPEAC CSW, Zagreb
  • 13 Sept 2017: High Performance Digital Systems and Applications Conference, Warwick UK
  • 22 Jan 2018: ECOSCALE ExaNeSt, ExaNoDe, EuroEXA ExascaleHPC workshop, HiPEAC conference, Manchester UK
  • 19 Jan 2018: DATE 2018, Dresden Germany
  • 24 Jan 2018: WRC 2018, Manchester UK
  • 28 May 2018: ECOSCALE, ExaNeSt, ExaNoDe, EuroEXA workshop, HPC Summit Week, Ljubljana
  • 21 Jan 2019: EuroExaScale workshop organized by ECOSCALE, HiPEAC 2019, Valencia, Spain
  • 21 Jan 2019: WRC 2019, Valencia, Iakovos Mavroidis, "UNILOGIC scalable heterogeneous HPC architecture"
  • 19 June 2019: Poster presentation, ISC 2019 exhibition, HiPEAC booth, Frankfurt, Germany
  • 20 June 2019: Panelist, ExaComm 2019 workshop, ISC 2019, Frankfurt, Germany

News


Contract Info

Contract Number: 671632

TIMETABLE:

- Starting date: 01/10/2015

- Duration: 36 months

BUDGET:

- Total cost: €4.237.000

- Funding: €4.237.000

Seventh Framework Programme
EUROPEAN COMMISSION